Socionext achieves perfect operation on the first attempt through LSI development based on the chip, package, and PCB co-design flow. While offering a good forecast for design through reference design, we develop and improve LSI models (IBIS, timing model, LSI power supply model) necessary for transmission line analysis of DDR4 and other memory interfaces and USB3.0 and other SerDes interfaces to achieve total optimization in each phase of design based on integrated chips, packages, and PCB analysis. This allows for an issue that used to only be discovered in the actual design phase to be addressed in the prototyping phase.
We offer customers IBIS and a timing model early on in the design stage so that they can conduct transmission line analysis taking timing into account.
The use of IBIS5.0 and an LSI power supply model (chip and package) for PCB power supply impedance analysis and SSO noise analysis allow customers to perform high accuracy development in a short TAT.